Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel method which aims at minimizing the total power consumption during testing. This paper presents a low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR ,called BS-LFSR. When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared to those patterns produced by a conventional LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications when compared with existing methods. The BS-LFSR is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (scan and capture) in the test cycle or while scanning out a response to a signature analyzer. Experimental results on ISCAS’89 benchmark circuits show up to 65% and 55% reductions in average and peak power, respectively.
