The heart of an on-chip network is the router, which undertakes crucial task of coordinating the data flow. A high speed on_chip router is designed and implemented in this paper. High speed is achieved by allowing routing function for each input port and high level of parallelism is achieved by using distributed arbiters. The designing has been done using the hardware description language VHDL in XILINX ISE tool. Its FPGA implementation is tested using Virtex-5 board.
